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Data Structures
Peripheral_registers_structures
CMSIS_Device » Stm32f439xx

Data Structures

struct  ADC_TypeDef
 Analog to Digital Converter. More...
 
struct  ADC_Common_TypeDef
 
struct  CAN_TxMailBox_TypeDef
 Controller Area Network TxMailBox. More...
 
struct  CAN_FIFOMailBox_TypeDef
 Controller Area Network FIFOMailBox. More...
 
struct  CAN_FilterRegister_TypeDef
 Controller Area Network FilterRegister. More...
 
struct  CAN_TypeDef
 Controller Area Network. More...
 
struct  CRC_TypeDef
 CRC calculation unit. More...
 
struct  DAC_TypeDef
 Digital to Analog Converter. More...
 
struct  DBGMCU_TypeDef
 Debug MCU. More...
 
struct  DCMI_TypeDef
 DCMI. More...
 
struct  DMA_Stream_TypeDef
 DMA Controller. More...
 
struct  DMA_TypeDef
 
struct  DMA2D_TypeDef
 DMA2D Controller. More...
 
struct  ETH_TypeDef
 Ethernet MAC. More...
 
struct  EXTI_TypeDef
 External Interrupt/Event Controller. More...
 
struct  FLASH_TypeDef
 FLASH Registers. More...
 
struct  FMC_Bank1_TypeDef
 Flexible Memory Controller. More...
 
struct  FMC_Bank1E_TypeDef
 Flexible Memory Controller Bank1E. More...
 
struct  FMC_Bank2_3_TypeDef
 Flexible Memory Controller Bank2. More...
 
struct  FMC_Bank4_TypeDef
 Flexible Memory Controller Bank4. More...
 
struct  FMC_Bank5_6_TypeDef
 Flexible Memory Controller Bank5_6. More...
 
struct  GPIO_TypeDef
 General Purpose I/O. More...
 
struct  SYSCFG_TypeDef
 System configuration controller. More...
 
struct  I2C_TypeDef
 Inter-integrated Circuit Interface. More...
 
struct  IWDG_TypeDef
 Independent WATCHDOG. More...
 
struct  LTDC_TypeDef
 LCD-TFT Display Controller. More...
 
struct  LTDC_Layer_TypeDef
 LCD-TFT Display layer x Controller. More...
 
struct  PWR_TypeDef
 Power Control. More...
 
struct  RCC_TypeDef
 Reset and Clock Control. More...
 
struct  RTC_TypeDef
 Real-Time Clock. More...
 
struct  SAI_TypeDef
 Serial Audio Interface. More...
 
struct  SAI_Block_TypeDef
 
struct  SDIO_TypeDef
 SD host Interface. More...
 
struct  SPI_TypeDef
 Serial Peripheral Interface. More...
 
struct  TIM_TypeDef
 TIM. More...
 
struct  USART_TypeDef
 Universal Synchronous Asynchronous Receiver Transmitter. More...
 
struct  WWDG_TypeDef
 Window WATCHDOG. More...
 
struct  CRYP_TypeDef
 Crypto Processor. More...
 
struct  HASH_TypeDef
 HASH. More...
 
struct  HASH_DIGEST_TypeDef
 HASH_DIGEST. More...
 
struct  RNG_TypeDef
 RNG. More...
 
struct  USB_OTG_GlobalTypeDef
 USB_OTG_Core_Registers. More...
 
struct  USB_OTG_DeviceTypeDef
 USB_OTG_device_Registers. More...
 
struct  USB_OTG_INEndpointTypeDef
 USB_OTG_IN_Endpoint-Specific_Register. More...
 
struct  USB_OTG_OUTEndpointTypeDef
 USB_OTG_OUT_Endpoint-Specific_Registers. More...
 
struct  USB_OTG_HostTypeDef
 USB_OTG_Host_Mode_Register_Structures. More...
 
struct  USB_OTG_HostChannelTypeDef
 USB_OTG_Host_Channel_Specific_Registers. More...
 

Detailed Description

Data Structure Documentation

◆ ADC_TypeDef

struct ADC_TypeDef

Analog to Digital Converter.

Definition at line 186 of file stm32f439xx.h.

Data Fields
__IO uint32_t SR

ADC status register, Address offset: 0x00

__IO uint32_t CR1

ADC control register 1, Address offset: 0x04

__IO uint32_t CR2

ADC control register 2, Address offset: 0x08

__IO uint32_t SMPR1

ADC sample time register 1, Address offset: 0x0C

__IO uint32_t SMPR2

ADC sample time register 2, Address offset: 0x10

__IO uint32_t JOFR1

ADC injected channel data offset register 1, Address offset: 0x14

__IO uint32_t JOFR2

ADC injected channel data offset register 2, Address offset: 0x18

__IO uint32_t JOFR3

ADC injected channel data offset register 3, Address offset: 0x1C

__IO uint32_t JOFR4

ADC injected channel data offset register 4, Address offset: 0x20

__IO uint32_t HTR

ADC watchdog higher threshold register, Address offset: 0x24

__IO uint32_t LTR

ADC watchdog lower threshold register, Address offset: 0x28

__IO uint32_t SQR1

ADC regular sequence register 1, Address offset: 0x2C

__IO uint32_t SQR2

ADC regular sequence register 2, Address offset: 0x30

__IO uint32_t SQR3

ADC regular sequence register 3, Address offset: 0x34

__IO uint32_t JSQR

ADC injected sequence register, Address offset: 0x38

__IO uint32_t JDR1

ADC injected data register 1, Address offset: 0x3C

__IO uint32_t JDR2

ADC injected data register 2, Address offset: 0x40

__IO uint32_t JDR3

ADC injected data register 3, Address offset: 0x44

__IO uint32_t JDR4

ADC injected data register 4, Address offset: 0x48

__IO uint32_t DR

ADC regular data register, Address offset: 0x4C

◆ ADC_Common_TypeDef

struct ADC_Common_TypeDef

Definition at line 210 of file stm32f439xx.h.

Data Fields
__IO uint32_t CSR

ADC Common status register, Address offset: ADC1 base address + 0x300

__IO uint32_t CCR

ADC common control register, Address offset: ADC1 base address + 0x304

__IO uint32_t CDR

ADC common regular data register for dual AND triple modes, Address offset: ADC1 base address + 0x308

◆ CAN_TxMailBox_TypeDef

struct CAN_TxMailBox_TypeDef

Controller Area Network TxMailBox.

Definition at line 223 of file stm32f439xx.h.

Data Fields
__IO uint32_t TIR

CAN TX mailbox identifier register

__IO uint32_t TDTR

CAN mailbox data length control and time stamp register

__IO uint32_t TDLR

CAN mailbox data low register

__IO uint32_t TDHR

CAN mailbox data high register

◆ CAN_FIFOMailBox_TypeDef

struct CAN_FIFOMailBox_TypeDef

Controller Area Network FIFOMailBox.

Definition at line 235 of file stm32f439xx.h.

Data Fields
__IO uint32_t RIR

CAN receive FIFO mailbox identifier register

__IO uint32_t RDTR

CAN receive FIFO mailbox data length control and time stamp register

__IO uint32_t RDLR

CAN receive FIFO mailbox data low register

__IO uint32_t RDHR

CAN receive FIFO mailbox data high register

◆ CAN_FilterRegister_TypeDef

struct CAN_FilterRegister_TypeDef

Controller Area Network FilterRegister.

Definition at line 247 of file stm32f439xx.h.

Data Fields
__IO uint32_t FR1

CAN Filter bank register 1

__IO uint32_t FR2

CAN Filter bank register 1

◆ CAN_TypeDef

struct CAN_TypeDef

Controller Area Network.

Definition at line 257 of file stm32f439xx.h.

Data Fields
__IO uint32_t MCR

CAN master control register, Address offset: 0x00

__IO uint32_t MSR

CAN master status register, Address offset: 0x04

__IO uint32_t TSR

CAN transmit status register, Address offset: 0x08

__IO uint32_t RF0R

CAN receive FIFO 0 register, Address offset: 0x0C

__IO uint32_t RF1R

CAN receive FIFO 1 register, Address offset: 0x10

__IO uint32_t IER

CAN interrupt enable register, Address offset: 0x14

__IO uint32_t ESR

CAN error status register, Address offset: 0x18

__IO uint32_t BTR

CAN bit timing register, Address offset: 0x1C

uint32_t RESERVED0[88]

Reserved, 0x020 - 0x17F

CAN_TxMailBox_TypeDef sTxMailBox[3]

CAN Tx MailBox, Address offset: 0x180 - 0x1AC

CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]

CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC

uint32_t RESERVED1[12]

Reserved, 0x1D0 - 0x1FF

__IO uint32_t FMR

CAN filter master register, Address offset: 0x200

__IO uint32_t FM1R

CAN filter mode register, Address offset: 0x204

uint32_t RESERVED2

Reserved, 0x208

__IO uint32_t FS1R

CAN filter scale register, Address offset: 0x20C

uint32_t RESERVED3

Reserved, 0x210

__IO uint32_t FFA1R

CAN filter FIFO assignment register, Address offset: 0x214

uint32_t RESERVED4

Reserved, 0x218

__IO uint32_t FA1R

CAN filter activation register, Address offset: 0x21C

uint32_t RESERVED5[8]

Reserved, 0x220-0x23F

CAN_FilterRegister_TypeDef sFilterRegister[28]

CAN Filter Register, Address offset: 0x240-0x31C

◆ CRC_TypeDef

struct CRC_TypeDef

CRC calculation unit.

Definition at line 287 of file stm32f439xx.h.

Data Fields
__IO uint32_t DR

CRC Data register, Address offset: 0x00

__IO uint8_t IDR

CRC Independent data register, Address offset: 0x04

uint8_t RESERVED0

Reserved, 0x05

uint16_t RESERVED1

Reserved, 0x06

__IO uint32_t CR

CRC Control register, Address offset: 0x08

◆ DAC_TypeDef

struct DAC_TypeDef

Digital to Analog Converter.

Definition at line 300 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR

DAC control register, Address offset: 0x00

__IO uint32_t SWTRIGR

DAC software trigger register, Address offset: 0x04

__IO uint32_t DHR12R1

DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08

__IO uint32_t DHR12L1

DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C

__IO uint32_t DHR8R1

DAC channel1 8-bit right aligned data holding register, Address offset: 0x10

__IO uint32_t DHR12R2

DAC channel2 12-bit right aligned data holding register, Address offset: 0x14

__IO uint32_t DHR12L2

DAC channel2 12-bit left aligned data holding register, Address offset: 0x18

__IO uint32_t DHR8R2

DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C

__IO uint32_t DHR12RD

Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20

__IO uint32_t DHR12LD

DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24

__IO uint32_t DHR8RD

DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28

__IO uint32_t DOR1

DAC channel1 data output register, Address offset: 0x2C

__IO uint32_t DOR2

DAC channel2 data output register, Address offset: 0x30

__IO uint32_t SR

DAC status register, Address offset: 0x34

◆ DBGMCU_TypeDef

struct DBGMCU_TypeDef

Debug MCU.

Definition at line 322 of file stm32f439xx.h.

Data Fields
__IO uint32_t IDCODE

MCU device ID code, Address offset: 0x00

__IO uint32_t CR

Debug MCU configuration register, Address offset: 0x04

__IO uint32_t APB1FZ

Debug MCU APB1 freeze register, Address offset: 0x08

__IO uint32_t APB2FZ

Debug MCU APB2 freeze register, Address offset: 0x0C

◆ DCMI_TypeDef

struct DCMI_TypeDef

DCMI.

Definition at line 334 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR

DCMI control register 1, Address offset: 0x00

__IO uint32_t SR

DCMI status register, Address offset: 0x04

__IO uint32_t RISR

DCMI raw interrupt status register, Address offset: 0x08

__IO uint32_t IER

DCMI interrupt enable register, Address offset: 0x0C

__IO uint32_t MISR

DCMI masked interrupt status register, Address offset: 0x10

__IO uint32_t ICR

DCMI interrupt clear register, Address offset: 0x14

__IO uint32_t ESCR

DCMI embedded synchronization code register, Address offset: 0x18

__IO uint32_t ESUR

DCMI embedded synchronization unmask register, Address offset: 0x1C

__IO uint32_t CWSTRTR

DCMI crop window start, Address offset: 0x20

__IO uint32_t CWSIZER

DCMI crop window size, Address offset: 0x24

__IO uint32_t DR

DCMI data register, Address offset: 0x28

◆ DMA_Stream_TypeDef

struct DMA_Stream_TypeDef

DMA Controller.

Definition at line 353 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR

DMA stream x configuration register

__IO uint32_t NDTR

DMA stream x number of data register

__IO uint32_t PAR

DMA stream x peripheral address register

__IO uint32_t M0AR

DMA stream x memory 0 address register

__IO uint32_t M1AR

DMA stream x memory 1 address register

__IO uint32_t FCR

DMA stream x FIFO control register

◆ DMA_TypeDef

struct DMA_TypeDef

Definition at line 363 of file stm32f439xx.h.

Data Fields
__IO uint32_t LISR

DMA low interrupt status register, Address offset: 0x00

__IO uint32_t HISR

DMA high interrupt status register, Address offset: 0x04

__IO uint32_t LIFCR

DMA low interrupt flag clear register, Address offset: 0x08

__IO uint32_t HIFCR

DMA high interrupt flag clear register, Address offset: 0x0C

◆ DMA2D_TypeDef

struct DMA2D_TypeDef

DMA2D Controller.

Definition at line 375 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR

DMA2D Control Register, Address offset: 0x00

__IO uint32_t ISR

DMA2D Interrupt Status Register, Address offset: 0x04

__IO uint32_t IFCR

DMA2D Interrupt Flag Clear Register, Address offset: 0x08

__IO uint32_t FGMAR

DMA2D Foreground Memory Address Register, Address offset: 0x0C

__IO uint32_t FGOR

DMA2D Foreground Offset Register, Address offset: 0x10

__IO uint32_t BGMAR

DMA2D Background Memory Address Register, Address offset: 0x14

__IO uint32_t BGOR

DMA2D Background Offset Register, Address offset: 0x18

__IO uint32_t FGPFCCR

DMA2D Foreground PFC Control Register, Address offset: 0x1C

__IO uint32_t FGCOLR

DMA2D Foreground Color Register, Address offset: 0x20

__IO uint32_t BGPFCCR

DMA2D Background PFC Control Register, Address offset: 0x24

__IO uint32_t BGCOLR

DMA2D Background Color Register, Address offset: 0x28

__IO uint32_t FGCMAR

DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C

__IO uint32_t BGCMAR

DMA2D Background CLUT Memory Address Register, Address offset: 0x30

__IO uint32_t OPFCCR

DMA2D Output PFC Control Register, Address offset: 0x34

__IO uint32_t OCOLR

DMA2D Output Color Register, Address offset: 0x38

__IO uint32_t OMAR

DMA2D Output Memory Address Register, Address offset: 0x3C

__IO uint32_t OOR

DMA2D Output Offset Register, Address offset: 0x40

__IO uint32_t NLR

DMA2D Number of Line Register, Address offset: 0x44

__IO uint32_t LWR

DMA2D Line Watermark Register, Address offset: 0x48

__IO uint32_t AMTCR

DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C

uint32_t RESERVED[236]

Reserved, 0x50-0x3FF

__IO uint32_t FGCLUT[256]

DMA2D Foreground CLUT, Address offset:400-7FF

__IO uint32_t BGCLUT[256]

DMA2D Background CLUT, Address offset:800-BFF

◆ ETH_TypeDef

struct ETH_TypeDef

Ethernet MAC.

Definition at line 406 of file stm32f439xx.h.

◆ EXTI_TypeDef

struct EXTI_TypeDef

External Interrupt/Event Controller.

Definition at line 481 of file stm32f439xx.h.

Data Fields
__IO uint32_t IMR

EXTI Interrupt mask register, Address offset: 0x00

__IO uint32_t EMR

EXTI Event mask register, Address offset: 0x04

__IO uint32_t RTSR

EXTI Rising trigger selection register, Address offset: 0x08

__IO uint32_t FTSR

EXTI Falling trigger selection register, Address offset: 0x0C

__IO uint32_t SWIER

EXTI Software interrupt event register, Address offset: 0x10

__IO uint32_t PR

EXTI Pending register, Address offset: 0x14

◆ FLASH_TypeDef

struct FLASH_TypeDef

FLASH Registers.

Definition at line 495 of file stm32f439xx.h.

Data Fields
__IO uint32_t ACR

FLASH access control register, Address offset: 0x00

__IO uint32_t KEYR

FLASH key register, Address offset: 0x04

__IO uint32_t OPTKEYR

FLASH option key register, Address offset: 0x08

__IO uint32_t SR

FLASH status register, Address offset: 0x0C

__IO uint32_t CR

FLASH control register, Address offset: 0x10

__IO uint32_t OPTCR

FLASH option control register , Address offset: 0x14

__IO uint32_t OPTCR1

FLASH option control register 1, Address offset: 0x18

◆ FMC_Bank1_TypeDef

struct FMC_Bank1_TypeDef

Flexible Memory Controller.

Definition at line 510 of file stm32f439xx.h.

Data Fields
__IO uint32_t BTCR[8]

NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C

◆ FMC_Bank1E_TypeDef

struct FMC_Bank1E_TypeDef

Flexible Memory Controller Bank1E.

Definition at line 519 of file stm32f439xx.h.

Data Fields
__IO uint32_t BWTR[7]

NOR/PSRAM write timing registers, Address offset: 0x104-0x11C

◆ FMC_Bank2_3_TypeDef

struct FMC_Bank2_3_TypeDef

Flexible Memory Controller Bank2.

Definition at line 527 of file stm32f439xx.h.

Data Fields
__IO uint32_t PCR2

NAND Flash control register 2, Address offset: 0x60

__IO uint32_t SR2

NAND Flash FIFO status and interrupt register 2, Address offset: 0x64

__IO uint32_t PMEM2

NAND Flash Common memory space timing register 2, Address offset: 0x68

__IO uint32_t PATT2

NAND Flash Attribute memory space timing register 2, Address offset: 0x6C

uint32_t RESERVED0

Reserved, 0x70

__IO uint32_t ECCR2

NAND Flash ECC result registers 2, Address offset: 0x74

uint32_t RESERVED1

Reserved, 0x78

uint32_t RESERVED2

Reserved, 0x7C

__IO uint32_t PCR3

NAND Flash control register 3, Address offset: 0x80

__IO uint32_t SR3

NAND Flash FIFO status and interrupt register 3, Address offset: 0x84

__IO uint32_t PMEM3

NAND Flash Common memory space timing register 3, Address offset: 0x88

__IO uint32_t PATT3

NAND Flash Attribute memory space timing register 3, Address offset: 0x8C

uint32_t RESERVED3

Reserved, 0x90

__IO uint32_t ECCR3

NAND Flash ECC result registers 3, Address offset: 0x94

◆ FMC_Bank4_TypeDef

struct FMC_Bank4_TypeDef

Flexible Memory Controller Bank4.

Definition at line 549 of file stm32f439xx.h.

Data Fields
__IO uint32_t PCR4

PC Card control register 4, Address offset: 0xA0

__IO uint32_t SR4

PC Card FIFO status and interrupt register 4, Address offset: 0xA4

__IO uint32_t PMEM4

PC Card Common memory space timing register 4, Address offset: 0xA8

__IO uint32_t PATT4

PC Card Attribute memory space timing register 4, Address offset: 0xAC

__IO uint32_t PIO4

PC Card I/O space timing register 4, Address offset: 0xB0

◆ FMC_Bank5_6_TypeDef

struct FMC_Bank5_6_TypeDef

Flexible Memory Controller Bank5_6.

Definition at line 562 of file stm32f439xx.h.

Data Fields
__IO uint32_t SDCR[2]

SDRAM Control registers , Address offset: 0x140-0x144

__IO uint32_t SDTR[2]

SDRAM Timing registers , Address offset: 0x148-0x14C

__IO uint32_t SDCMR

SDRAM Command Mode register, Address offset: 0x150

__IO uint32_t SDRTR

SDRAM Refresh Timer register, Address offset: 0x154

__IO uint32_t SDSR

SDRAM Status register, Address offset: 0x158

◆ GPIO_TypeDef

struct GPIO_TypeDef

General Purpose I/O.

Definition at line 575 of file stm32f439xx.h.

Data Fields
__IO uint32_t MODER

GPIO port mode register, Address offset: 0x00

__IO uint32_t OTYPER

GPIO port output type register, Address offset: 0x04

__IO uint32_t OSPEEDR

GPIO port output speed register, Address offset: 0x08

__IO uint32_t PUPDR

GPIO port pull-up/pull-down register, Address offset: 0x0C

__IO uint32_t IDR

GPIO port input data register, Address offset: 0x10

__IO uint32_t ODR

GPIO port output data register, Address offset: 0x14

__IO uint32_t BSRR

GPIO port bit set/reset register, Address offset: 0x18

__IO uint32_t LCKR

GPIO port configuration lock register, Address offset: 0x1C

__IO uint32_t AFR[2]

GPIO alternate function registers, Address offset: 0x20-0x24

◆ SYSCFG_TypeDef

struct SYSCFG_TypeDef

System configuration controller.

Definition at line 592 of file stm32f439xx.h.

Data Fields
__IO uint32_t MEMRMP

SYSCFG memory remap register, Address offset: 0x00

__IO uint32_t PMC

SYSCFG peripheral mode configuration register, Address offset: 0x04

__IO uint32_t EXTICR[4]

SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14

uint32_t RESERVED[2]

Reserved, 0x18-0x1C

__IO uint32_t CMPCR

SYSCFG Compensation cell control register, Address offset: 0x20

◆ I2C_TypeDef

struct I2C_TypeDef

Inter-integrated Circuit Interface.

Definition at line 605 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR1

I2C Control register 1, Address offset: 0x00

__IO uint32_t CR2

I2C Control register 2, Address offset: 0x04

__IO uint32_t OAR1

I2C Own address register 1, Address offset: 0x08

__IO uint32_t OAR2

I2C Own address register 2, Address offset: 0x0C

__IO uint32_t DR

I2C Data register, Address offset: 0x10

__IO uint32_t SR1

I2C Status register 1, Address offset: 0x14

__IO uint32_t SR2

I2C Status register 2, Address offset: 0x18

__IO uint32_t CCR

I2C Clock control register, Address offset: 0x1C

__IO uint32_t TRISE

I2C TRISE register, Address offset: 0x20

__IO uint32_t FLTR

I2C FLTR register, Address offset: 0x24

◆ IWDG_TypeDef

struct IWDG_TypeDef

Independent WATCHDOG.

Definition at line 623 of file stm32f439xx.h.

Data Fields
__IO uint32_t KR

IWDG Key register, Address offset: 0x00

__IO uint32_t PR

IWDG Prescaler register, Address offset: 0x04

__IO uint32_t RLR

IWDG Reload register, Address offset: 0x08

__IO uint32_t SR

IWDG Status register, Address offset: 0x0C

◆ LTDC_TypeDef

struct LTDC_TypeDef

LCD-TFT Display Controller.

Definition at line 635 of file stm32f439xx.h.

Data Fields
uint32_t RESERVED0[2]

Reserved, 0x00-0x04

__IO uint32_t SSCR

LTDC Synchronization Size Configuration Register, Address offset: 0x08

__IO uint32_t BPCR

LTDC Back Porch Configuration Register, Address offset: 0x0C

__IO uint32_t AWCR

LTDC Active Width Configuration Register, Address offset: 0x10

__IO uint32_t TWCR

LTDC Total Width Configuration Register, Address offset: 0x14

__IO uint32_t GCR

LTDC Global Control Register, Address offset: 0x18

uint32_t RESERVED1[2]

Reserved, 0x1C-0x20

__IO uint32_t SRCR

LTDC Shadow Reload Configuration Register, Address offset: 0x24

uint32_t RESERVED2[1]

Reserved, 0x28

__IO uint32_t BCCR

LTDC Background Color Configuration Register, Address offset: 0x2C

uint32_t RESERVED3[1]

Reserved, 0x30

__IO uint32_t IER

LTDC Interrupt Enable Register, Address offset: 0x34

__IO uint32_t ISR

LTDC Interrupt Status Register, Address offset: 0x38

__IO uint32_t ICR

LTDC Interrupt Clear Register, Address offset: 0x3C

__IO uint32_t LIPCR

LTDC Line Interrupt Position Configuration Register, Address offset: 0x40

__IO uint32_t CPSR

LTDC Current Position Status Register, Address offset: 0x44

__IO uint32_t CDSR

LTDC Current Display Status Register, Address offset: 0x48

◆ LTDC_Layer_TypeDef

struct LTDC_Layer_TypeDef

LCD-TFT Display layer x Controller.

Definition at line 660 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR

LTDC Layerx Control Register Address offset: 0x84

__IO uint32_t WHPCR

LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88

__IO uint32_t WVPCR

LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C

__IO uint32_t CKCR

LTDC Layerx Color Keying Configuration Register Address offset: 0x90

__IO uint32_t PFCR

LTDC Layerx Pixel Format Configuration Register Address offset: 0x94

__IO uint32_t CACR

LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98

__IO uint32_t DCCR

LTDC Layerx Default Color Configuration Register Address offset: 0x9C

__IO uint32_t BFCR

LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0

uint32_t RESERVED0[2]

Reserved

__IO uint32_t CFBAR

LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC

__IO uint32_t CFBLR

LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0

__IO uint32_t CFBLNR

LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4

uint32_t RESERVED1[3]

Reserved

__IO uint32_t CLUTWR

LTDC Layerx CLUT Write Register Address offset: 0x144

◆ PWR_TypeDef

struct PWR_TypeDef

Power Control.

Definition at line 682 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR

PWR power control register, Address offset: 0x00

__IO uint32_t CSR

PWR power control/status register, Address offset: 0x04

◆ RCC_TypeDef

struct RCC_TypeDef

Reset and Clock Control.

Definition at line 692 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR

RCC clock control register, Address offset: 0x00

__IO uint32_t PLLCFGR

RCC PLL configuration register, Address offset: 0x04

__IO uint32_t CFGR

RCC clock configuration register, Address offset: 0x08

__IO uint32_t CIR

RCC clock interrupt register, Address offset: 0x0C

__IO uint32_t AHB1RSTR

RCC AHB1 peripheral reset register, Address offset: 0x10

__IO uint32_t AHB2RSTR

RCC AHB2 peripheral reset register, Address offset: 0x14

__IO uint32_t AHB3RSTR

RCC AHB3 peripheral reset register, Address offset: 0x18

uint32_t RESERVED0

Reserved, 0x1C

__IO uint32_t APB1RSTR

RCC APB1 peripheral reset register, Address offset: 0x20

__IO uint32_t APB2RSTR

RCC APB2 peripheral reset register, Address offset: 0x24

uint32_t RESERVED1[2]

Reserved, 0x28-0x2C

__IO uint32_t AHB1ENR

RCC AHB1 peripheral clock register, Address offset: 0x30

__IO uint32_t AHB2ENR

RCC AHB2 peripheral clock register, Address offset: 0x34

__IO uint32_t AHB3ENR

RCC AHB3 peripheral clock register, Address offset: 0x38

uint32_t RESERVED2

Reserved, 0x3C

__IO uint32_t APB1ENR

RCC APB1 peripheral clock enable register, Address offset: 0x40

__IO uint32_t APB2ENR

RCC APB2 peripheral clock enable register, Address offset: 0x44

uint32_t RESERVED3[2]

Reserved, 0x48-0x4C

__IO uint32_t AHB1LPENR

RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50

__IO uint32_t AHB2LPENR

RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54

__IO uint32_t AHB3LPENR

RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58

uint32_t RESERVED4

Reserved, 0x5C

__IO uint32_t APB1LPENR

RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60

__IO uint32_t APB2LPENR

RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64

uint32_t RESERVED5[2]

Reserved, 0x68-0x6C

__IO uint32_t BDCR

RCC Backup domain control register, Address offset: 0x70

__IO uint32_t CSR

RCC clock control & status register, Address offset: 0x74

uint32_t RESERVED6[2]

Reserved, 0x78-0x7C

__IO uint32_t SSCGR

RCC spread spectrum clock generation register, Address offset: 0x80

__IO uint32_t PLLI2SCFGR

RCC PLLI2S configuration register, Address offset: 0x84

__IO uint32_t PLLSAICFGR

RCC PLLSAI configuration register, Address offset: 0x88

__IO uint32_t DCKCFGR

RCC Dedicated Clocks configuration register, Address offset: 0x8C

◆ RTC_TypeDef

struct RTC_TypeDef

Real-Time Clock.

Definition at line 732 of file stm32f439xx.h.

Data Fields
__IO uint32_t TR

RTC time register, Address offset: 0x00

__IO uint32_t DR

RTC date register, Address offset: 0x04

__IO uint32_t CR

RTC control register, Address offset: 0x08

__IO uint32_t ISR

RTC initialization and status register, Address offset: 0x0C

__IO uint32_t PRER

RTC prescaler register, Address offset: 0x10

__IO uint32_t WUTR

RTC wakeup timer register, Address offset: 0x14

__IO uint32_t CALIBR

RTC calibration register, Address offset: 0x18

__IO uint32_t ALRMAR

RTC alarm A register, Address offset: 0x1C

__IO uint32_t ALRMBR

RTC alarm B register, Address offset: 0x20

__IO uint32_t WPR

RTC write protection register, Address offset: 0x24

__IO uint32_t SSR

RTC sub second register, Address offset: 0x28

__IO uint32_t SHIFTR

RTC shift control register, Address offset: 0x2C

__IO uint32_t TSTR

RTC time stamp time register, Address offset: 0x30

__IO uint32_t TSDR

RTC time stamp date register, Address offset: 0x34

__IO uint32_t TSSSR

RTC time-stamp sub second register, Address offset: 0x38

__IO uint32_t CALR

RTC calibration register, Address offset: 0x3C

__IO uint32_t TAFCR

RTC tamper and alternate function configuration register, Address offset: 0x40

__IO uint32_t ALRMASSR

RTC alarm A sub second register, Address offset: 0x44

__IO uint32_t ALRMBSSR

RTC alarm B sub second register, Address offset: 0x48

uint32_t RESERVED7

Reserved, 0x4C

__IO uint32_t BKP0R

RTC backup register 1, Address offset: 0x50

__IO uint32_t BKP1R

RTC backup register 1, Address offset: 0x54

__IO uint32_t BKP2R

RTC backup register 2, Address offset: 0x58

__IO uint32_t BKP3R

RTC backup register 3, Address offset: 0x5C

__IO uint32_t BKP4R

RTC backup register 4, Address offset: 0x60

__IO uint32_t BKP5R

RTC backup register 5, Address offset: 0x64

__IO uint32_t BKP6R

RTC backup register 6, Address offset: 0x68

__IO uint32_t BKP7R

RTC backup register 7, Address offset: 0x6C

__IO uint32_t BKP8R

RTC backup register 8, Address offset: 0x70

__IO uint32_t BKP9R

RTC backup register 9, Address offset: 0x74

__IO uint32_t BKP10R

RTC backup register 10, Address offset: 0x78

__IO uint32_t BKP11R

RTC backup register 11, Address offset: 0x7C

__IO uint32_t BKP12R

RTC backup register 12, Address offset: 0x80

__IO uint32_t BKP13R

RTC backup register 13, Address offset: 0x84

__IO uint32_t BKP14R

RTC backup register 14, Address offset: 0x88

__IO uint32_t BKP15R

RTC backup register 15, Address offset: 0x8C

__IO uint32_t BKP16R

RTC backup register 16, Address offset: 0x90

__IO uint32_t BKP17R

RTC backup register 17, Address offset: 0x94

__IO uint32_t BKP18R

RTC backup register 18, Address offset: 0x98

__IO uint32_t BKP19R

RTC backup register 19, Address offset: 0x9C

◆ SAI_TypeDef

struct SAI_TypeDef

Serial Audio Interface.

Definition at line 780 of file stm32f439xx.h.

Data Fields
__IO uint32_t GCR

SAI global configuration register, Address offset: 0x00

◆ SAI_Block_TypeDef

struct SAI_Block_TypeDef

Definition at line 785 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR1

SAI block x configuration register 1, Address offset: 0x04

__IO uint32_t CR2

SAI block x configuration register 2, Address offset: 0x08

__IO uint32_t FRCR

SAI block x frame configuration register, Address offset: 0x0C

__IO uint32_t SLOTR

SAI block x slot register, Address offset: 0x10

__IO uint32_t IMR

SAI block x interrupt mask register, Address offset: 0x14

__IO uint32_t SR

SAI block x status register, Address offset: 0x18

__IO uint32_t CLRFR

SAI block x clear flag register, Address offset: 0x1C

__IO uint32_t DR

SAI block x data register, Address offset: 0x20

◆ SDIO_TypeDef

struct SDIO_TypeDef

SD host Interface.

Definition at line 801 of file stm32f439xx.h.

Data Fields
__IO uint32_t POWER

SDIO power control register, Address offset: 0x00

__IO uint32_t CLKCR

SDI clock control register, Address offset: 0x04

__IO uint32_t ARG

SDIO argument register, Address offset: 0x08

__IO uint32_t CMD

SDIO command register, Address offset: 0x0C

__IO const uint32_t RESPCMD

SDIO command response register, Address offset: 0x10

__IO const uint32_t RESP1

SDIO response 1 register, Address offset: 0x14

__IO const uint32_t RESP2

SDIO response 2 register, Address offset: 0x18

__IO const uint32_t RESP3

SDIO response 3 register, Address offset: 0x1C

__IO const uint32_t RESP4

SDIO response 4 register, Address offset: 0x20

__IO uint32_t DTIMER

SDIO data timer register, Address offset: 0x24

__IO uint32_t DLEN

SDIO data length register, Address offset: 0x28

__IO uint32_t DCTRL

SDIO data control register, Address offset: 0x2C

__IO const uint32_t DCOUNT

SDIO data counter register, Address offset: 0x30

__IO const uint32_t STA

SDIO status register, Address offset: 0x34

__IO uint32_t ICR

SDIO interrupt clear register, Address offset: 0x38

__IO uint32_t MASK

SDIO mask register, Address offset: 0x3C

uint32_t RESERVED0[2]

Reserved, 0x40-0x44

__IO const uint32_t FIFOCNT

SDIO FIFO counter register, Address offset: 0x48

uint32_t RESERVED1[13]

Reserved, 0x4C-0x7C

__IO uint32_t FIFO

SDIO data FIFO register, Address offset: 0x80

◆ SPI_TypeDef

struct SPI_TypeDef

Serial Peripheral Interface.

Definition at line 829 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR1

SPI control register 1 (not used in I2S mode), Address offset: 0x00

__IO uint32_t CR2

SPI control register 2, Address offset: 0x04

__IO uint32_t SR

SPI status register, Address offset: 0x08

__IO uint32_t DR

SPI data register, Address offset: 0x0C

__IO uint32_t CRCPR

SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10

__IO uint32_t RXCRCR

SPI RX CRC register (not used in I2S mode), Address offset: 0x14

__IO uint32_t TXCRCR

SPI TX CRC register (not used in I2S mode), Address offset: 0x18

__IO uint32_t I2SCFGR

SPI_I2S configuration register, Address offset: 0x1C

__IO uint32_t I2SPR

SPI_I2S prescaler register, Address offset: 0x20

◆ TIM_TypeDef

struct TIM_TypeDef

TIM.

Definition at line 847 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR1

TIM control register 1, Address offset: 0x00

__IO uint32_t CR2

TIM control register 2, Address offset: 0x04

__IO uint32_t SMCR

TIM slave mode control register, Address offset: 0x08

__IO uint32_t DIER

TIM DMA/interrupt enable register, Address offset: 0x0C

__IO uint32_t SR

TIM status register, Address offset: 0x10

__IO uint32_t EGR

TIM event generation register, Address offset: 0x14

__IO uint32_t CCMR1

TIM capture/compare mode register 1, Address offset: 0x18

__IO uint32_t CCMR2

TIM capture/compare mode register 2, Address offset: 0x1C

__IO uint32_t CCER

TIM capture/compare enable register, Address offset: 0x20

__IO uint32_t CNT

TIM counter register, Address offset: 0x24

__IO uint32_t PSC

TIM prescaler, Address offset: 0x28

__IO uint32_t ARR

TIM auto-reload register, Address offset: 0x2C

__IO uint32_t RCR

TIM repetition counter register, Address offset: 0x30

__IO uint32_t CCR1

TIM capture/compare register 1, Address offset: 0x34

__IO uint32_t CCR2

TIM capture/compare register 2, Address offset: 0x38

__IO uint32_t CCR3

TIM capture/compare register 3, Address offset: 0x3C

__IO uint32_t CCR4

TIM capture/compare register 4, Address offset: 0x40

__IO uint32_t BDTR

TIM break and dead-time register, Address offset: 0x44

__IO uint32_t DCR

TIM DMA control register, Address offset: 0x48

__IO uint32_t DMAR

TIM DMA address for full transfer, Address offset: 0x4C

__IO uint32_t OR

TIM option register, Address offset: 0x50

◆ USART_TypeDef

struct USART_TypeDef

Universal Synchronous Asynchronous Receiver Transmitter.

Definition at line 876 of file stm32f439xx.h.

Data Fields
__IO uint32_t SR

USART Status register, Address offset: 0x00

__IO uint32_t DR

USART Data register, Address offset: 0x04

__IO uint32_t BRR

USART Baud rate register, Address offset: 0x08

__IO uint32_t CR1

USART Control register 1, Address offset: 0x0C

__IO uint32_t CR2

USART Control register 2, Address offset: 0x10

__IO uint32_t CR3

USART Control register 3, Address offset: 0x14

__IO uint32_t GTPR

USART Guard time and prescaler register, Address offset: 0x18

◆ WWDG_TypeDef

struct WWDG_TypeDef

Window WATCHDOG.

Definition at line 891 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR

WWDG Control register, Address offset: 0x00

__IO uint32_t CFR

WWDG Configuration register, Address offset: 0x04

__IO uint32_t SR

WWDG Status register, Address offset: 0x08

◆ CRYP_TypeDef

struct CRYP_TypeDef

Crypto Processor.

Definition at line 902 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR

CRYP control register, Address offset: 0x00

__IO uint32_t SR

CRYP status register, Address offset: 0x04

__IO uint32_t DIN

CRYP data input register, Address offset: 0x08

__IO uint32_t DOUT

CRYP data output register, Address offset: 0x0C

__IO uint32_t DMACR

CRYP DMA control register, Address offset: 0x10

__IO uint32_t IMSCR

CRYP interrupt mask set/clear register, Address offset: 0x14

__IO uint32_t RISR

CRYP raw interrupt status register, Address offset: 0x18

__IO uint32_t MISR

CRYP masked interrupt status register, Address offset: 0x1C

__IO uint32_t K0LR

CRYP key left register 0, Address offset: 0x20

__IO uint32_t K0RR

CRYP key right register 0, Address offset: 0x24

__IO uint32_t K1LR

CRYP key left register 1, Address offset: 0x28

__IO uint32_t K1RR

CRYP key right register 1, Address offset: 0x2C

__IO uint32_t K2LR

CRYP key left register 2, Address offset: 0x30

__IO uint32_t K2RR

CRYP key right register 2, Address offset: 0x34

__IO uint32_t K3LR

CRYP key left register 3, Address offset: 0x38

__IO uint32_t K3RR

CRYP key right register 3, Address offset: 0x3C

__IO uint32_t IV0LR

CRYP initialization vector left-word register 0, Address offset: 0x40

__IO uint32_t IV0RR

CRYP initialization vector right-word register 0, Address offset: 0x44

__IO uint32_t IV1LR

CRYP initialization vector left-word register 1, Address offset: 0x48

__IO uint32_t IV1RR

CRYP initialization vector right-word register 1, Address offset: 0x4C

__IO uint32_t CSGCMCCM0R

CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50

__IO uint32_t CSGCMCCM1R

CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54

__IO uint32_t CSGCMCCM2R

CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58

__IO uint32_t CSGCMCCM3R

CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C

__IO uint32_t CSGCMCCM4R

CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60

__IO uint32_t CSGCMCCM5R

CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64

__IO uint32_t CSGCMCCM6R

CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68

__IO uint32_t CSGCMCCM7R

CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C

__IO uint32_t CSGCM0R

CRYP GCM/GMAC context swap register 0, Address offset: 0x70

__IO uint32_t CSGCM1R

CRYP GCM/GMAC context swap register 1, Address offset: 0x74

__IO uint32_t CSGCM2R

CRYP GCM/GMAC context swap register 2, Address offset: 0x78

__IO uint32_t CSGCM3R

CRYP GCM/GMAC context swap register 3, Address offset: 0x7C

__IO uint32_t CSGCM4R

CRYP GCM/GMAC context swap register 4, Address offset: 0x80

__IO uint32_t CSGCM5R

CRYP GCM/GMAC context swap register 5, Address offset: 0x84

__IO uint32_t CSGCM6R

CRYP GCM/GMAC context swap register 6, Address offset: 0x88

__IO uint32_t CSGCM7R

CRYP GCM/GMAC context swap register 7, Address offset: 0x8C

◆ HASH_TypeDef

struct HASH_TypeDef

HASH.

Definition at line 946 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR

HASH control register, Address offset: 0x00

__IO uint32_t DIN

HASH data input register, Address offset: 0x04

__IO uint32_t STR

HASH start register, Address offset: 0x08

__IO uint32_t HR[5]

HASH digest registers, Address offset: 0x0C-0x1C

__IO uint32_t IMR

HASH interrupt enable register, Address offset: 0x20

__IO uint32_t SR

HASH status register, Address offset: 0x24

uint32_t RESERVED[52]

Reserved, 0x28-0xF4

__IO uint32_t CSR[54]

HASH context swap registers, Address offset: 0x0F8-0x1CC

◆ HASH_DIGEST_TypeDef

struct HASH_DIGEST_TypeDef

HASH_DIGEST.

Definition at line 962 of file stm32f439xx.h.

Data Fields
__IO uint32_t HR[8]

HASH digest registers, Address offset: 0x310-0x32C

◆ RNG_TypeDef

struct RNG_TypeDef

RNG.

Definition at line 971 of file stm32f439xx.h.

Data Fields
__IO uint32_t CR

RNG control register, Address offset: 0x00

__IO uint32_t SR

RNG status register, Address offset: 0x04

__IO uint32_t DR

RNG data register, Address offset: 0x08

◆ USB_OTG_GlobalTypeDef

struct USB_OTG_GlobalTypeDef

USB_OTG_Core_Registers.

Definition at line 981 of file stm32f439xx.h.

Data Fields
__IO uint32_t GOTGCTL

USB_OTG Control and Status Register 000h

__IO uint32_t GOTGINT

USB_OTG Interrupt Register 004h

__IO uint32_t GAHBCFG

Core AHB Configuration Register 008h

__IO uint32_t GUSBCFG

Core USB Configuration Register 00Ch

__IO uint32_t GRSTCTL

Core Reset Register 010h

__IO uint32_t GINTSTS

Core Interrupt Register 014h

__IO uint32_t GINTMSK

Core Interrupt Mask Register 018h

__IO uint32_t GRXSTSR

Receive Sts Q Read Register 01Ch

__IO uint32_t GRXSTSP

Receive Sts Q Read & POP Register 020h

__IO uint32_t GRXFSIZ

Receive FIFO Size Register 024h

__IO uint32_t DIEPTXF0_HNPTXFSIZ

EP0 / Non Periodic Tx FIFO Size Register 028h

__IO uint32_t HNPTXSTS

Non Periodic Tx FIFO/Queue Sts reg 02Ch

uint32_t Reserved30[2]

Reserved 030h

__IO uint32_t GCCFG

General Purpose IO Register 038h

__IO uint32_t CID

User ID Register 03Ch

uint32_t Reserved40[48]

Reserved 0x40-0xFF

__IO uint32_t HPTXFSIZ

Host Periodic Tx FIFO Size Reg 100h

__IO uint32_t DIEPTXF[0x0F]

dev Periodic Transmit FIFO

◆ USB_OTG_DeviceTypeDef

struct USB_OTG_DeviceTypeDef

USB_OTG_device_Registers.

Definition at line 1006 of file stm32f439xx.h.

Data Fields
__IO uint32_t DCFG

dev Configuration Register 800h

__IO uint32_t DCTL

dev Control Register 804h

__IO uint32_t DSTS

dev Status Register (RO) 808h

uint32_t Reserved0C

Reserved 80Ch

__IO uint32_t DIEPMSK

dev IN Endpoint Mask 810h

__IO uint32_t DOEPMSK

dev OUT Endpoint Mask 814h

__IO uint32_t DAINT

dev All Endpoints Itr Reg 818h

__IO uint32_t DAINTMSK

dev All Endpoints Itr Mask 81Ch

uint32_t Reserved20

Reserved 820h

uint32_t Reserved9

Reserved 824h

__IO uint32_t DVBUSDIS

dev VBUS discharge Register 828h

__IO uint32_t DVBUSPULSE

dev VBUS Pulse Register 82Ch

__IO uint32_t DTHRCTL

dev threshold 830h

__IO uint32_t DIEPEMPMSK

dev empty msk 834h

__IO uint32_t DEACHINT

dedicated EP interrupt 838h

__IO uint32_t DEACHMSK

dedicated EP msk 83Ch

uint32_t Reserved40

dedicated EP mask 840h

__IO uint32_t DINEP1MSK

dedicated EP mask 844h

uint32_t Reserved44[15]

Reserved 844-87Ch

__IO uint32_t DOUTEP1MSK

dedicated EP msk 884h

◆ USB_OTG_INEndpointTypeDef

struct USB_OTG_INEndpointTypeDef

USB_OTG_IN_Endpoint-Specific_Register.

Definition at line 1033 of file stm32f439xx.h.

Data Fields
__IO uint32_t DIEPCTL

dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h

uint32_t Reserved04

Reserved 900h + (ep_num * 20h) + 04h

__IO uint32_t DIEPINT

dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h

uint32_t Reserved0C

Reserved 900h + (ep_num * 20h) + 0Ch

__IO uint32_t DIEPTSIZ

IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h

__IO uint32_t DIEPDMA

IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h

__IO uint32_t DTXFSTS

IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h

uint32_t Reserved18

Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch

◆ USB_OTG_OUTEndpointTypeDef

struct USB_OTG_OUTEndpointTypeDef

USB_OTG_OUT_Endpoint-Specific_Registers.

Definition at line 1048 of file stm32f439xx.h.

Data Fields
__IO uint32_t DOEPCTL

dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h

uint32_t Reserved04

Reserved B00h + (ep_num * 20h) + 04h

__IO uint32_t DOEPINT

dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h

uint32_t Reserved0C

Reserved B00h + (ep_num * 20h) + 0Ch

__IO uint32_t DOEPTSIZ

dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h

__IO uint32_t DOEPDMA

dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h

uint32_t Reserved18[2]

Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch

◆ USB_OTG_HostTypeDef

struct USB_OTG_HostTypeDef

USB_OTG_Host_Mode_Register_Structures.

Definition at line 1062 of file stm32f439xx.h.

Data Fields
__IO uint32_t HCFG

Host Configuration Register 400h

__IO uint32_t HFIR

Host Frame Interval Register 404h

__IO uint32_t HFNUM

Host Frame Nbr/Frame Remaining 408h

uint32_t Reserved40C

Reserved 40Ch

__IO uint32_t HPTXSTS

Host Periodic Tx FIFO/ Queue Status 410h

__IO uint32_t HAINT

Host All Channels Interrupt Register 414h

__IO uint32_t HAINTMSK

Host All Channels Interrupt Mask 418h

◆ USB_OTG_HostChannelTypeDef

struct USB_OTG_HostChannelTypeDef

USB_OTG_Host_Channel_Specific_Registers.

Definition at line 1076 of file stm32f439xx.h.

Data Fields
__IO uint32_t HCCHAR

Host Channel Characteristics Register 500h

__IO uint32_t HCSPLT

Host Channel Split Control Register 504h

__IO uint32_t HCINT

Host Channel Interrupt Register 508h

__IO uint32_t HCINTMSK

Host Channel Interrupt Mask Register 50Ch

__IO uint32_t HCTSIZ

Host Channel Transfer Size Register 510h

__IO uint32_t HCDMA

Host Channel DMA Address Register 514h

uint32_t Reserved[2]

Reserved