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Peripheral_memory_map
CMSIS_Device » Stm32f439xx

Macros

#define FLASH_BASE   0x08000000UL
 
#define CCMDATARAM_BASE   0x10000000UL
 
#define SRAM1_BASE   0x20000000UL
 
#define SRAM2_BASE   0x2001C000UL
 
#define SRAM3_BASE   0x20020000UL
 
#define PERIPH_BASE   0x40000000UL
 
#define BKPSRAM_BASE   0x40024000UL
 
#define FMC_R_BASE   0xA0000000UL
 
#define SRAM1_BB_BASE   0x22000000UL
 
#define SRAM2_BB_BASE   0x22380000UL
 
#define SRAM3_BB_BASE   0x22400000UL
 
#define PERIPH_BB_BASE   0x42000000UL
 
#define BKPSRAM_BB_BASE   0x42480000UL
 
#define FLASH_END   0x081FFFFFUL
 
#define FLASH_OTP_BASE   0x1FFF7800UL
 
#define FLASH_OTP_END   0x1FFF7A0FUL
 
#define CCMDATARAM_END   0x1000FFFFUL
 
#define SRAM_BB_BASE   SRAM1_BB_BASE
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00UL)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104UL)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000UL)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800UL)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140UL)
 
#define DBGMCU_BASE   0xE0042000UL
 
#define UID_BASE   0x1FFF7A10UL
 
#define FLASHSIZE_BASE   0x1FFF7A22UL
 
#define PACKAGE_BASE   0x1FFF7BF0UL
 

Detailed Description

Macro Definition Documentation

◆ FLASH_BASE

#define FLASH_BASE   0x08000000UL

FLASH(up to 2 MB) base address in the alias region

Definition at line 1094 of file stm32f439xx.h.

◆ CCMDATARAM_BASE

#define CCMDATARAM_BASE   0x10000000UL

CCM(core coupled memory) data RAM(64 KB) base address in the alias region

Definition at line 1095 of file stm32f439xx.h.

◆ SRAM1_BASE

#define SRAM1_BASE   0x20000000UL

SRAM1(112 KB) base address in the alias region

Definition at line 1096 of file stm32f439xx.h.

◆ SRAM2_BASE

#define SRAM2_BASE   0x2001C000UL

SRAM2(16 KB) base address in the alias region

Definition at line 1097 of file stm32f439xx.h.

◆ SRAM3_BASE

#define SRAM3_BASE   0x20020000UL

SRAM3(64 KB) base address in the alias region

Definition at line 1098 of file stm32f439xx.h.

◆ PERIPH_BASE

#define PERIPH_BASE   0x40000000UL

Peripheral base address in the alias region

Definition at line 1099 of file stm32f439xx.h.

◆ BKPSRAM_BASE

#define BKPSRAM_BASE   0x40024000UL

Backup SRAM(4 KB) base address in the alias region

Definition at line 1100 of file stm32f439xx.h.

◆ FMC_R_BASE

#define FMC_R_BASE   0xA0000000UL

FMC registers base address

Definition at line 1101 of file stm32f439xx.h.

◆ SRAM1_BB_BASE

#define SRAM1_BB_BASE   0x22000000UL

SRAM1(112 KB) base address in the bit-band region

Definition at line 1102 of file stm32f439xx.h.

◆ SRAM2_BB_BASE

#define SRAM2_BB_BASE   0x22380000UL

SRAM2(16 KB) base address in the bit-band region

Definition at line 1103 of file stm32f439xx.h.

◆ SRAM3_BB_BASE

#define SRAM3_BB_BASE   0x22400000UL

SRAM3(64 KB) base address in the bit-band region

Definition at line 1104 of file stm32f439xx.h.

◆ PERIPH_BB_BASE

#define PERIPH_BB_BASE   0x42000000UL

Peripheral base address in the bit-band region

Definition at line 1105 of file stm32f439xx.h.

◆ BKPSRAM_BB_BASE

#define BKPSRAM_BB_BASE   0x42480000UL

Backup SRAM(4 KB) base address in the bit-band region

Definition at line 1106 of file stm32f439xx.h.

◆ FLASH_END

#define FLASH_END   0x081FFFFFUL

FLASH end address

Definition at line 1107 of file stm32f439xx.h.

◆ FLASH_OTP_BASE

#define FLASH_OTP_BASE   0x1FFF7800UL

Base address of : (up to 528 Bytes) embedded FLASH OTP Area

Definition at line 1108 of file stm32f439xx.h.

◆ FLASH_OTP_END

#define FLASH_OTP_END   0x1FFF7A0FUL

End address of : (up to 528 Bytes) embedded FLASH OTP Area

Definition at line 1109 of file stm32f439xx.h.

◆ CCMDATARAM_END

#define CCMDATARAM_END   0x1000FFFFUL

CCM data RAM end address

Definition at line 1110 of file stm32f439xx.h.

◆ SRAM_BB_BASE

#define SRAM_BB_BASE   SRAM1_BB_BASE

Peripheral memory map

Definition at line 1114 of file stm32f439xx.h.

◆ AHB2PERIPH_BASE

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)

APB1 peripherals

Definition at line 1120 of file stm32f439xx.h.

◆ UART8_BASE

#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00UL)

APB2 peripherals

Definition at line 1151 of file stm32f439xx.h.

◆ LTDC_Layer2_BASE

#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104UL)

AHB1 peripherals

Definition at line 1179 of file stm32f439xx.h.

◆ DMA2D_BASE

#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000UL)

AHB2 peripherals

Definition at line 1219 of file stm32f439xx.h.

◆ RNG_BASE

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800UL)

FMC Bankx registers base address

Definition at line 1226 of file stm32f439xx.h.

◆ FMC_Bank5_6_R_BASE

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140UL)

Debug MCU registers base address

Definition at line 1233 of file stm32f439xx.h.

◆ DBGMCU_BASE

#define DBGMCU_BASE   0xE0042000UL

USB registers base address

Definition at line 1237 of file stm32f439xx.h.

◆ UID_BASE

#define UID_BASE   0x1FFF7A10UL

Unique device ID register base address

Definition at line 1255 of file stm32f439xx.h.

◆ FLASHSIZE_BASE

#define FLASHSIZE_BASE   0x1FFF7A22UL

FLASH Size register base address

Definition at line 1256 of file stm32f439xx.h.

◆ PACKAGE_BASE

#define PACKAGE_BASE   0x1FFF7BF0UL

Package size register base address

Definition at line 1257 of file stm32f439xx.h.