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drivers.c
1#include "drivers.h"
2
3// ===============================================================
4// RCC INITIALISATION
5// ===============================================================
6
7// configure RCC APB1 : CAN1, CAN2, UART3, SPI2, SPI3, TIM6, TIM7,
8void configure_RCC_APB1(void) {
9 RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN | RCC_APB1ENR_USART3EN | RCC_APB1ENR_SPI3EN | RCC_APB1ENR_SPI2EN | RCC_APB1ENR_TIM6EN | RCC_APB1ENR_TIM7EN);
10 RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST | RCC_APB1RSTR_CAN2RST | RCC_APB1RSTR_USART3RST | RCC_APB1RSTR_SPI3RST | RCC_APB1RSTR_SPI2RST | RCC_APB1RSTR_TIM6RST | RCC_APB1RSTR_TIM7RST);
11 __ASM("NOP");
12 __ASM("NOP");
13 RCC->APB1RSTR &= (uint16_t)(~(RCC_APB1RSTR_CAN1RST | RCC_APB1RSTR_CAN2RST | RCC_APB1RSTR_USART3RST | RCC_APB1RSTR_SPI3RST | RCC_APB1RSTR_SPI2RST | RCC_APB1RSTR_TIM6RST | RCC_APB1RSTR_TIM7RST));
14 __ASM("NOP");
15 __ASM("NOP");
16}
17
18// configure RCC APB2 : SPI1, USART6
19void configure_RCC_APB2(void) {
20 RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN | RCC_APB2ENR_USART6EN | RCC_APB2ENR_SPI4EN | RCC_APB2ENR_SYSCFGEN);
21 RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST | RCC_APB2RSTR_USART6RST | RCC_APB2RSTR_SPI4RST | RCC_APB2RSTR_SYSCFGRST);
22 __ASM("NOP");
23 __ASM("NOP");
24 RCC->APB2RSTR &= (uint16_t)(~(RCC_APB2RSTR_SPI1RST | RCC_APB2RSTR_USART6RST | RCC_APB2RSTR_SPI4RST | RCC_APB2RSTR_SYSCFGRST));
25 __ASM("NOP");
26 __ASM("NOP");
27}
28
29// configure RCC AHB1 GPIO A, B, C, D, E
30void configure_RCC_AHB1(void) {
31 RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN);
32 RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST | RCC_AHB1RSTR_GPIOBRST | RCC_AHB1RSTR_GPIOCRST | RCC_AHB1RSTR_GPIODRST | RCC_AHB1RSTR_GPIOERST);
33 __ASM("NOP");
34 __ASM("NOP");
35 RCC->AHB1RSTR &= (uint16_t)(~(RCC_AHB1RSTR_GPIOARST | RCC_AHB1RSTR_GPIOBRST | RCC_AHB1RSTR_GPIOCRST | RCC_AHB1RSTR_GPIODRST | RCC_AHB1RSTR_GPIOERST));
36}
37
38// ===============================================================
39// FLASH
40// ===============================================================
41
42void configure_SPI4_Flash(void) {
43 GPIOE->MODER &= (~(GPIO_MODER_MODE12_Msk | GPIO_MODER_MODE13_Msk | GPIO_MODER_MODE14_Msk));
44 GPIOE->MODER |= ((0x2 << GPIO_MODER_MODE12_Pos) | (0x2 << GPIO_MODER_MODE13_Pos) | (0x2 << GPIO_MODER_MODE14_Pos));
45 GPIOE->AFR[1] &= (uint32_t)(~(0x0FFFF000)); // clears AFRH 11, 12, 13 and 14
46 GPIOE->AFR[1] |= (0x05555000); // sets AFRH 10, 11 and 12 to AF6 for lora SPI
47 GPIOE->MODER &= (~(GPIO_MODER_MODE9_Msk | GPIO_MODER_MODE10_Msk | GPIO_MODER_MODE11_Msk));
48 GPIOE->MODER |= ((0x1 << GPIO_MODER_MODE9_Pos) | (0x1 << GPIO_MODER_MODE10_Pos) | (0x1 << GPIO_MODER_MODE11_Pos));
49 GPIOE->OTYPER &= (uint16_t)(~(GPIO_OTYPER_OT9 | GPIO_OTYPER_OT10 | GPIO_OTYPER_OT11));
50 GPIOE->OSPEEDR &= (~(GPIO_OSPEEDR_OSPEED9_Msk | GPIO_OSPEEDR_OSPEED10_Msk | GPIO_OSPEEDR_OSPEED11_Msk));
51 GPIOE->OSPEEDR |= ((0x2 << GPIO_OSPEEDR_OSPEED9_Pos) | (0x2 << GPIO_OSPEEDR_OSPEED10_Pos) | (0x2 << GPIO_OSPEEDR_OSPEED11_Pos));
52 GPIOE->OTYPER &= (~(GPIO_OTYPER_OT12 | GPIO_OTYPER_OT13 | GPIO_OTYPER_OT14));
53 GPIOE->OSPEEDR &= (~(GPIO_OSPEEDR_OSPEED12_Msk | GPIO_OSPEEDR_OSPEED13_Msk | GPIO_OSPEEDR_OSPEED14_Msk));
54 GPIOE->OSPEEDR |= (0x2 << GPIO_OSPEEDR_OSPEED12_Pos | 0x2 << GPIO_OSPEEDR_OSPEED13_Pos | 0x2 << GPIO_OSPEEDR_OSPEED14_Pos);
55 GPIOE->ODR |= (GPIO_ODR_OD10) | (GPIO_ODR_OD11) | (GPIO_ODR_OD9);
56 SPI4->CR1 &= (~(SPI_CR1_BR_Msk));
57 SPI4->CR1 &= (~(SPI_CR1_CPHA_Msk) | (SPI_CR1_CPOL_Msk));
58 SPI4->CR1 |= SPI_CR1_MSTR; // micro is master
59 SPI4->CR1 |= SPI_CR1_SSM | SPI_CR1_SSI; // Software management
60 SPI4->CR1 &= (~(SPI_CR1_LSBFIRST_Msk)); // MSB FIRST
61 SPI4->CR1 &= ~(SPI_CR1_BIDIMODE | SPI_CR1_RXONLY);
62 SPI4->CR1 &= (~(SPI_CR1_BR_Msk));
63 SPI4->CR1 |= ((0x00 << SPI_CR1_BR_Pos));
64 SPI4->CR1 |= (0x1 << SPI_CR1_SPE_Pos);
65}
66
67// ===============================================================
68// COMMUNICATIONS
69// ===============================================================
70
71void configure_SPI3_LoRa() {
72 GPIOC->MODER &= (~(GPIO_MODER_MODE10_Msk | GPIO_MODER_MODE11_Msk | GPIO_MODER_MODE12_Msk));
73 GPIOC->MODER |= ((0x2 << GPIO_MODER_MODE10_Pos) | (0x2 << GPIO_MODER_MODE11_Pos) | (0x2 << GPIO_MODER_MODE12_Pos));
74 GPIOC->PUPDR &= (~(GPIO_PUPDR_PUPD10_Msk | GPIO_PUPDR_PUPD11_Msk | GPIO_PUPDR_PUPD12_Msk));
75 GPIOC->PUPDR |= ((0X1 << GPIO_PUPDR_PUPD10_Pos) | (0X1 << GPIO_PUPDR_PUPD11_Pos) | (0X1 << GPIO_PUPDR_PUPD12_Pos));
76 GPIOD->PUPDR |= (0X1 << GPIO_PUPDR_PUPD1_Pos);
77 GPIOD->MODER &= (~(GPIO_MODER_MODE0_Msk) | (GPIO_MODER_MODE7_Msk) | (GPIO_MODER_MODE1_Msk));
78 GPIOD->MODER |= (0X01 << GPIO_MODER_MODE0_Pos) | (0X01 << GPIO_MODER_MODE7_Pos); // chip select stuff
79 TIM6->ARR &= (~(TIM_ARR_ARR_Msk));
80 TIM6->PSC &= (~(TIM_PSC_PSC_Msk));
81 TIM6->ARR |= 20000;
82 TIM6->PSC |= 251;
83
84 GPIOD->ODR |= (GPIO_ODR_OD7);
85 TIM6->CR1 |= TIM_CR1_CEN;
86 while ((TIM6->SR & TIM_SR_UIF) == 0); // 60 ms delay
87 GPIOD->ODR &= (~(GPIO_ODR_OD7));
88 TIM6->SR &= ~(TIM_SR_UIF); // clears UIF
89
90 GPIOC->OTYPER &= (~(GPIO_OTYPER_OT10 | GPIO_OTYPER_OT11 | GPIO_OTYPER_OT12));
91 GPIOC->OSPEEDR &= (~(GPIO_OSPEEDR_OSPEED10_Msk | GPIO_OSPEEDR_OSPEED11_Msk | GPIO_OSPEEDR_OSPEED12_Msk));
92 GPIOC->OSPEEDR |= (0x2 << GPIO_OSPEEDR_OSPEED10_Pos | 0x2 << GPIO_OSPEEDR_OSPEED11_Pos | 0x2 << GPIO_OSPEEDR_OSPEED12_Pos);
93 GPIOD->ODR |= GPIO_ODR_OD0; // raise chip select
94 GPIOC->AFR[1] &= (uint32_t)(~(0x000FFF00)); // clears AFRH 10, 11 and 12
95 GPIOC->AFR[1] |= (0x00066600); // sets AFRH 10, 11 and 12 to AF6 for lora SPI
96
97 SPI3->CR1 &= (~(SPI_CR1_BR_Msk));
98 SPI3->CR1 |= (0x2 << SPI_CR1_BR_Pos); // set board rate too fclck / 16 = 42/8 = 5.25 (10 MHz max for LoRa)
99 SPI3->CR1 &= (~(SPI_CR1_CPHA_Msk) | (SPI_CR1_CPOL_Msk)); // sets CPOL and CPHA to zero as specified in LoRa datasheet
100 // needs bit DIO and Reset configured to idk what
101 SPI3->CR1 |= SPI_CR1_MSTR; // micro is master
102 SPI3->CR1 |= SPI_CR1_SSM | SPI_CR1_SSI; // Software management
103 SPI3->CR1 &= (~(SPI_CR1_LSBFIRST_Msk)); // MSB FIRST
104 SPI3->CR1 |= SPI_CR1_DFF;
105 SPI3->CR1 &= ~(SPI_CR1_BIDIMODE | SPI_CR1_RXONLY);
106 SPI3->CR1 |= (0x1 << SPI_CR1_SPE_Pos);
107}
108
109// ===============================================================
110// UART AND GPIO
111// ===============================================================
112
113void configure_UART3_GPS(void) {
114 GPIOD->MODER &= (~(GPIO_MODER_MODE8_Msk | GPIO_MODER_MODE9_Msk | GPIO_MODER_MODE13_Msk));
115 GPIOD->MODER |= ((0x2 << GPIO_MODER_MODE8_Pos) | (0x2 << GPIO_MODER_MODE9_Pos) | (0x1 << GPIO_MODER_MODE13_Pos));
116 GPIOD->AFR[1] &= (uint32_t)(~(0x000000FF)); // clears AFRL 6 and 7
117 GPIOD->AFR[1] |= (0x00000077); // sets PD 8, 9 and 13 to AF7
118
119 GPIOD->PUPDR |= (0X1 << GPIO_PUPDR_PUPD9_Pos);
120
121 GPIOD->OSPEEDR &= (~(GPIO_OSPEEDR_OSPEED8 | GPIO_OSPEEDR_OSPEED9 | GPIO_OSPEEDR_OSPEED13));
122 GPIOD->OSPEEDR |= (0x3 << GPIO_OSPEEDR_OSPEED8_Pos) | (0x3 << GPIO_OSPEEDR_OSPEED9_Pos) | (0x3 << GPIO_OSPEEDR_OSPEED13_Pos);
123
124 // need over sampling = 1
125 USART3->BRR &= (unsigned int)(0xFFFF0000); // clear mantissa and div in baud rate reg
126 USART3->BRR |= (0x0002227); // set mantissa and div in baud rate reg to 9600
127
128 USART3->CR1 &= (unsigned int)(~(0x400)); // disable parity
129 USART3->CR2 &= (unsigned int)(~(0xE00)); // disable synchrnous mode
130 USART3->CR3 &= (unsigned int)(~(0x300)); // disable flow control
131 USART3->CR1 |= (unsigned int)(0x200C); // enable usart, enable receive and transmitt
132 USART3->CR1 |= USART_CR1_OVER8;
133
134 // turn reset pin high
135 GPIOD->ODR |= GPIO_ODR_OD13;
136}
137
138// General GPIO Configure for MISC: LED1, LED2, Piezo Buzzer (PD14, PD15, PB15 respectivley)
139void configure_MISC_GPIO(void) {
140 GPIOD->MODER &= (~(GPIO_MODER_MODE14_Msk | GPIO_MODER_MODE15_Msk));
141 GPIOD->MODER |= ((0x1 << GPIO_MODER_MODE14_Pos) | (0x1 << GPIO_MODER_MODE15_Pos));
142 GPIOD->OTYPER &= (uint16_t)(~(GPIO_OTYPER_OT14 | GPIO_OTYPER_OT15)); // sets 0xboth as push-pull
143 GPIOD->OSPEEDR &= (~(GPIO_OSPEEDR_OSPEED14_Msk | GPIO_OSPEEDR_OSPEED15_Msk)); // clears Port 14 and 15 section
144 GPIOD->OSPEEDR |= ((0x2 << GPIO_OSPEEDR_OSPEED14_Pos) | (0x2 << GPIO_OSPEEDR_OSPEED15_Pos)); // sets slew rate as high speed
145
146 // GPIOD->PUPDR &= (~(GPIO_PUPDR_PUPD14 | GPIO_PUPDR_PUPD15)); // clears register for port 14 and 15
147 // GPIOD->PUPDR |= (0x00<<GPIO_PUPDR_PUPD14_Pos | 0x00<<GPIO_PUPDR_PUPD15_Pos ); // shifts 00 into and pos for 14 and 15
148 GPIOD->ODR &= (~(GPIO_ODR_OD14 | GPIO_ODR_OD15)); // turns LEDs off
149
150 GPIOB->MODER &= (~(GPIO_MODER_MODE15_Pos)); // clears pos 15 of port B moder R reg
151 GPIOB->MODER |= (0x1 << GPIO_MODER_MODE15_Pos); // sets pos 15 to general purpose output
152 GPIOB->OTYPER &= (~(GPIO_OTYPER_OT15_Msk)); // sets port B 15 to push-pull
153 GPIOB->OSPEEDR &= (~(GPIO_OSPEEDR_OSPEED15_Msk)); // clears pos 15 in Ospeed R reg
154 GPIOB->OSPEEDR |= (0x2 << GPIO_OSPEEDR_OSPEED15_Pos); // sets slew rate to highspeed
155 GPIOB->ODR &= (~(GPIO_ODR_OD15)); // turns peizer buzzer IO to low
156
157 // configure PB1 as input for B switch
158 GPIOB->MODER &= (~(GPIO_MODER_MODE1_Pos));
159 GPIOB->OTYPER &= (~(GPIO_OTYPER_OT1_Msk)); // sets port B 15 to push-pull
160 GPIOB->OSPEEDR &= (~(GPIO_OSPEEDR_OSPEED1_Msk)); // clears pos 15 in Ospeed R reg
161 GPIOB->OSPEEDR |= (0x2 << GPIO_OSPEEDR_OSPEED1_Pos); // sets slew rate to highspeed
162 GPIOB->PUPDR &= (~(GPIO_PUPDR_PUPD1)); // clears PUPDR for PB1
163 GPIOB->PUPDR |= (0x01 << GPIO_PUPDR_PUPD1_Pos); // set pull up resistor for PB1
164}
165
166// ===============================================================
167// TIMERS
168// ===============================================================
169
170void TIM6init(void) {
171 RCC->APB1ENR |= RCC_APB1ENR_TIM6EN;
172 RCC->APB1RSTR |= RCC_APB1RSTR_TIM6RST;
173 __asm("NOP");
174 __asm("NOP");
175 RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST);
176 __asm("NOP");
177 __asm("NOP");
178 TIM6->CR1 |= TIM_CR1_OPM;
179// TIM6->PSC |= 20;
180// TIM6->ARR &= (~(TIM_ARR_ARR_Msk));
181// TIM6->ARR |= 0X20; // 0.0005S delay
182}
183
184void TIM7init(void) {
185 RCC->APB1ENR |= RCC_APB1ENR_TIM7EN;
186 RCC->APB1RSTR |= RCC_APB1RSTR_TIM7RST;
187 __asm("NOP");
188 __asm("NOP");
189 RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST);
190 __asm("NOP");
191 __asm("NOP");
192 TIM7->CR1 |= TIM_CR1_OPM;
193 TIM7->PSC |= 1399;
194 TIM7->ARR &= (~(TIM_ARR_ARR_Msk));
195 TIM7->ARR |= 60000; // 1s delay
196}
197
198// ===============================================================
199// MISC
200// ===============================================================
201
202void buzzer(int count) {
203 TIM6->ARR &= (~(TIM_ARR_ARR_Msk));
204 TIM6->PSC &= (~(TIM_PSC_PSC_Msk));
205 TIM6->ARR |= 26123;
206 TIM6->PSC |= 0;
207 TIM6->CR1 |= TIM_CR1_CEN; // ensures timer is enabled
208 GPIOB->ODR |= 0x8000;
209
210 for(long i = 0; i < count; i++) {
211 GPIOB->ODR ^= 0x8000;
212 while ((TIM6->SR & TIM_SR_UIF) == 0);
213 TIM6->SR &= ~(TIM_SR_UIF); // clears UIF
214 TIM6->ARR |= 26123;
215 TIM6->CR1 |= TIM_CR1_CEN; // Enables counter
216 }
217
218}