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adc.h
1
9
10// ALLOW FORMATTING
11#ifndef ADC_H
12#define ADC_H
13
14#include "stm32f439xx.h"
15#include "stdint.h"
16#include "stdbool.h"
17
18// Macro definitions for pin config literals
19//
20
25#define ADC_CONFIG_DEFAULT \
26 (ADC_Config) { \
27 .RES = ADC_RES_12, \
28 .AWDEN = false, \
29 .JAWDEN = false, \
30 .EOCIE = false, \
31 .AWDIE = false, \
32 .JEOCIE = false, \
33 .SCAN = false, \
34 .ALIGN = ADC_ALIGN_RIGHT, \
35 .EOCS = ADC_EOCS_SINGLE, \
36 .DMA = false, \
37 .CONT = false, \
38 .HTR = 0, \
39 .LTR = 0, \
40 .L = 0, \
41 .JL = 0, \
42 .TSVREFE = false, \
43 .VBATE = true, \
44 .ADCPRE = ADC_ADCPRE_PCLK2_DIV2, \
45 }
46// clang-format off
47
53#define ADC_CR1_CONFIG_MASK ( \
54 ADC_CR1_RES \
55 | ADC_CR1_AWDEN \
56 | ADC_CR1_JAWDEN \
57 | ADC_CR1_AWDSGL \
58 | ADC_CR1_SCAN \
59 | ADC_CR1_JEOCIE \
60 | ADC_CR1_AWDIE \
61 | ADC_CR1_EOCIE \
62 | ADC_CR1_AWDCH \
63)
64
70#define ADC_CR2_CONFIG_MASK ( \
71 ADC_CR2_ALIGN \
72 | ADC_CR2_EOCS \
73 | ADC_CR2_DMA \
74 | ADC_CR2_CONT \
75)
76
82#define ADC_SMPR2_CONFIG_MASK ( \
83 ADC_SMPR2_SMP0 \
84 | ADC_SMPR2_SMP1 \
85 | ADC_SMPR2_SMP2 \
86 | ADC_SMPR2_SMP3 \
87 | ADC_SMPR2_SMP4 \
88 | ADC_SMPR2_SMP5 \
89 | ADC_SMPR2_SMP6 \
90 | ADC_SMPR2_SMP7 \
91 | ADC_SMPR2_SMP8 \
92 | ADC_SMPR2_SMP9 \
93)
99#define ADC_SMPR1_CONFIG_MASK ( \
100 ADC_SMPR1_SMP10 \
101 | ADC_SMPR1_SMP11 \
102 | ADC_SMPR1_SMP12 \
103 | ADC_SMPR1_SMP13 \
104 | ADC_SMPR1_SMP14 \
105 | ADC_SMPR1_SMP15 \
106 | ADC_SMPR1_SMP16 \
107 | ADC_SMPR1_SMP17 \
108 | ADC_SMPR1_SMP18 \
109)
110
116#define ADC_SQR3_CONFIG_MASK ( \
117 ADC_SQR3_SQ1 \
118 | ADC_SQR3_SQ2 \
119 | ADC_SQR3_SQ3 \
120 | ADC_SQR3_SQ4 \
121 | ADC_SQR3_SQ5 \
122 | ADC_SQR3_SQ6 \
123)
124
130#define ADC_SQR2_CONFIG_MASK ( \
131 ADC_SQR2_SQ7 \
132 | ADC_SQR2_SQ8 \
133 | ADC_SQR2_SQ9 \
134 | ADC_SQR2_SQ10 \
135 | ADC_SQR2_SQ11 \
136 | ADC_SQR2_SQ12 \
137)
138
144#define ADC_SQR1_CONFIG_MASK ( \
145 ADC_SQR1_SQ13 \
146 | ADC_SQR1_SQ14 \
147 | ADC_SQR1_SQ15 \
148 | ADC_SQR1_SQ16 \
149 | ADC_SQR1_L \
150)
151
157#define ADC_JSQR_CONFIG_MASK ( \
158 ADC_JSQR_JSQ1 \
159 | ADC_JSQR_JSQ2 \
160 | ADC_JSQR_JSQ3 \
161 | ADC_JSQR_JSQ4 \
162 | ADC_JSQR_JL \
163)
164// clang-format on
165
172
198
210
219
228
245
270
281
290
321
326typedef struct _ADC {
327 ADC_TypeDef *interface;
329 bool (*updateConfig)(struct _ADC *adc, ADC_Config *config);
330 bool (*startConversion)(struct _ADC *adc, ADC_ConversionType type);
331 uint16_t (*readData)(struct _ADC *adc);
332} ADC_t;
333
334ADC_t ADC_init(ADC_TypeDef *adc_regs, ADC_Config *config);
336uint16_t ADC_readData(ADC_t *adc);
337bool ADC_updateConfig(ADC_t *adc, ADC_Config *config);
338
340#endif
bool(* startConversion)(struct _ADC *adc, ADC_ConversionType type)
Function pointer to start an ADC conversion (regular or injected).
Definition adc.h:330
bool DMA
Direct Memory Access mode enable for regular channels (CR2.DMA).
Definition adc.h:308
ADC_Config config
Current configuration of the ADC peripheral.
Definition adc.h:328
ADC_Prescale ADCPRE
ADC prescaler for ADCCLK (ADC_CCR.ADCPRE).
Definition adc.h:319
bool AWDSGL
Analog Watchdog on single channel (true) or all (false) (CR1.AWDSGL).
Definition adc.h:303
uint16_t LTR
Analog watchdog lower threshold (LTR). Value should be 12-bit.
Definition adc.h:312
bool EOCIE
Interrupt Enable for End Of regular Conversion (CR1.EOCIE).
Definition adc.h:300
ADC_EocSelect EOCS
End Of Conversion Selection (CR2.EOCS).
Definition adc.h:307
bool VBATE
VBAT channel enable (ADC_CCR.VBATE).
Definition adc.h:318
ADC_Align ALIGN
Data alignment (CR2.ALIGN).
Definition adc.h:306
bool SCAN
Scan mode enable for regular channels (CR1.SCAN).
Definition adc.h:304
ADC_SequenceLength JL
Injected channel sequence length (1 to 4 conversions) (JSQR.JL).
Definition adc.h:315
uint16_t(* readData)(struct _ADC *adc)
Function pointer to read the ADC regular conversion result.
Definition adc.h:331
bool AWDEN
Analog Watchdog Enable on regular channels (CR1.AWDEN).
Definition adc.h:298
ADC_TypeDef * interface
Pointer to the STM32 ADC peripheral register map (e.g., ADC1).
Definition adc.h:327
bool AWDIE
Interrupt Enable for Analog Watchdog (CR1.AWDIE).
Definition adc.h:301
bool CONT
Continuous conversion mode for regular channels (CR2.CONT).
Definition adc.h:309
bool JAWDEN
Analog Watchdog Enable on injected channels (CR1.JAWDEN).
Definition adc.h:299
bool(* updateConfig)(struct _ADC *adc, ADC_Config *config)
Function pointer to update the ADC configuration.
Definition adc.h:329
ADC_Resolution RES
Resolution of the ADC (CR1.RES).
Definition adc.h:297
ADC_Channel SQ[16]
Regular channel sequence definition (SQ1 to SQ16) (SQR1, SQR2, SQR3).
Definition adc.h:314
ADC_SampleTime SMP[19]
Sampling time for each channel (0-18) (SMPR1, SMPR2).
Definition adc.h:310
bool JEOCIE
Interrupt Enable for End Of Injected Conversion (CR1.JEOCIE).
Definition adc.h:302
ADC_Channel JSQ[4]
Injected channel sequence definition (JSQ1 to JSQ4) (JSQR).
Definition adc.h:316
ADC_Channel AWDCH
Analog Watchdog Channel Select (if AWDSGL is true) (CR1.AWDCH).
Definition adc.h:305
bool TSVREFE
Temperature sensor and VREFINT enable (ADC_CCR.TSVREFE).
Definition adc.h:317
ADC_SequenceLength L
Regular channel sequence length (1 to 16 conversions) (SQR1.L).
Definition adc.h:313
uint16_t HTR
Analog watchdog higher threshold (HTR). Value should be 12-bit.
Definition adc.h:311
ADC_t ADC_init(ADC_TypeDef *adc_regs, ADC_Config *config)
Definition adc.c:23
ADC_SampleTime
ADC channel sample time enumeration.
Definition adc.h:235
uint16_t ADC_readData(ADC_t *adc)
Reads the data from the last ADC regular conversion.
Definition adc.c:201
ADC_Resolution
ADC conversion resolution enumeration.
Definition adc.h:204
ADC_Prescale
ADC prescaler selection enumeration.
Definition adc.h:275
ADC_Align
ADC data alignment enumeration.
Definition adc.h:215
bool ADC_startConversion(ADC_t *adc, ADC_ConversionType type)
Starts a regular ADC conversion.
Definition adc.c:170
bool ADC_updateConfig(ADC_t *adc, ADC_Config *config)
Update ADC peripheral configuration.
Definition adc.c:225
ADC_SequenceLength
ADC regular channel sequence length enumeration.
Definition adc.h:252
ADC_ConversionType
ADC conversion type enumeration.
Definition adc.h:286
ADC_Channel
ADC input channels enumeration.
Definition adc.h:177
ADC_EocSelect
ADC End of Conversion (EOC) selection enumeration.
Definition adc.h:224
@ ADC_SMP_144
144 ADC clock cycles
Definition adc.h:242
@ ADC_SMP_112
112 ADC clock cycles
Definition adc.h:241
@ ADC_SMP_84
84 ADC clock cycles
Definition adc.h:240
@ ADC_SMP_480
480 ADC clock cycles
Definition adc.h:243
@ ADC_SMP_3
3 ADC clock cycles
Definition adc.h:236
@ ADC_SMP_15
15 ADC clock cycles
Definition adc.h:237
@ ADC_SMP_28
28 ADC clock cycles
Definition adc.h:238
@ ADC_SMP_56
56 ADC clock cycles
Definition adc.h:239
@ ADC_RES_6
6-bit resolution
Definition adc.h:208
@ ADC_RES_8
8-bit resolution
Definition adc.h:207
@ ADC_RES_10
10-bit resolution
Definition adc.h:206
@ ADC_RES_12
12-bit resolution
Definition adc.h:205
@ ADC_ADCPRE_PCLK2_DIV6
ADCCLK = PCLK2 divided by 6.
Definition adc.h:278
@ ADC_ADCPRE_PCLK2_DIV4
ADCCLK = PCLK2 divided by 4.
Definition adc.h:277
@ ADC_ADCPRE_PCLK2_DIV8
ADCCLK = PCLK2 divided by 8.
Definition adc.h:279
@ ADC_ADCPRE_PCLK2_DIV2
ADCCLK = PCLK2 divided by 2.
Definition adc.h:276
@ ADC_ALIGN_RIGHT
Data is right-aligned in the ADC_DR register.
Definition adc.h:216
@ ADC_ALIGN_LEFT
Data is left-aligned in the ADC_DR register.
Definition adc.h:217
@ ADC_L1
1 conversion in the regular sequence
Definition adc.h:253
@ ADC_L5
5 conversions in the regular sequence
Definition adc.h:257
@ ADC_L9
9 conversions in the regular sequence
Definition adc.h:261
@ ADC_L6
6 conversions in the regular sequence
Definition adc.h:258
@ ADC_L11
11 conversions in the regular sequence
Definition adc.h:263
@ ADC_L8
8 conversions in the regular sequence
Definition adc.h:260
@ ADC_L10
10 conversions in the regular sequence
Definition adc.h:262
@ ADC_L14
14 conversions in the regular sequence
Definition adc.h:266
@ ADC_L2
2 conversions in the regular sequence
Definition adc.h:254
@ ADC_L12
12 conversions in the regular sequence
Definition adc.h:264
@ ADC_L15
15 conversions in the regular sequence
Definition adc.h:267
@ ADC_L7
7 conversions in the regular sequence
Definition adc.h:259
@ ADC_L3
3 conversions in the regular sequence
Definition adc.h:255
@ ADC_L16
16 conversions in the regular sequence
Definition adc.h:268
@ ADC_L4
4 conversions in the regular sequence
Definition adc.h:256
@ ADC_L13
13 conversions in the regular sequence
Definition adc.h:265
@ ADC_CONVERSION_REGULAR
Start a regular group conversion.
Definition adc.h:287
@ ADC_CONVERSION_INJECTED
Start an injected group conversion.
Definition adc.h:288
@ ADC_IN7
Analog input channel 7.
Definition adc.h:185
@ ADC_IN16
Analog input channel 16.
Definition adc.h:194
@ ADC_IN15
Analog input channel 15.
Definition adc.h:193
@ ADC_IN6
Analog input channel 6.
Definition adc.h:184
@ ADC_IN0
Analog input channel 0.
Definition adc.h:178
@ ADC_IN8
Analog input channel 8.
Definition adc.h:186
@ ADC_IN17
Analog input channel 17.
Definition adc.h:195
@ ADC_IN9
Analog input channel 9.
Definition adc.h:187
@ ADC_IN14
Analog input channel 14.
Definition adc.h:192
@ ADC_IN11
Analog input channel 11.
Definition adc.h:189
@ ADC_IN13
Analog input channel 13.
Definition adc.h:191
@ ADC_IN18
Analog input channel 18.
Definition adc.h:196
@ ADC_IN3
Analog input channel 3.
Definition adc.h:181
@ ADC_IN12
Analog input channel 12.
Definition adc.h:190
@ ADC_IN10
Analog input channel 10.
Definition adc.h:188
@ ADC_IN1
Analog input channel 1.
Definition adc.h:179
@ ADC_IN2
Analog input channel 2.
Definition adc.h:180
@ ADC_IN4
Analog input channel 4.
Definition adc.h:182
@ ADC_IN5
Analog input channel 5.
Definition adc.h:183
@ ADC_EOCS_SEQUENCE
EOC flag is set at the end of a sequence of regular conversions.
Definition adc.h:225
@ ADC_EOCS_SINGLE
EOC flag is set at the end of each single regular conversion.
Definition adc.h:226
ADC configuration structure.
Definition adc.h:296
Struct definition for ADC interface. Provides the API handle for consumers to interact with an ADC pe...
Definition adc.h:326