14#include "stm32f439xx.h"
25#define ADC_CONFIG_DEFAULT \
34 .ALIGN = ADC_ALIGN_RIGHT, \
35 .EOCS = ADC_EOCS_SINGLE, \
44 .ADCPRE = ADC_ADCPRE_PCLK2_DIV2, \
53#define ADC_CR1_CONFIG_MASK ( \
70#define ADC_CR2_CONFIG_MASK ( \
82#define ADC_SMPR2_CONFIG_MASK ( \
99#define ADC_SMPR1_CONFIG_MASK ( \
116#define ADC_SQR3_CONFIG_MASK ( \
130#define ADC_SQR2_CONFIG_MASK ( \
144#define ADC_SQR1_CONFIG_MASK ( \
157#define ADC_JSQR_CONFIG_MASK ( \
bool(* startConversion)(struct _ADC *adc, ADC_ConversionType type)
Function pointer to start an ADC conversion (regular or injected).
bool DMA
Direct Memory Access mode enable for regular channels (CR2.DMA).
ADC_Config config
Current configuration of the ADC peripheral.
ADC_Prescale ADCPRE
ADC prescaler for ADCCLK (ADC_CCR.ADCPRE).
bool AWDSGL
Analog Watchdog on single channel (true) or all (false) (CR1.AWDSGL).
uint16_t LTR
Analog watchdog lower threshold (LTR). Value should be 12-bit.
bool EOCIE
Interrupt Enable for End Of regular Conversion (CR1.EOCIE).
ADC_EocSelect EOCS
End Of Conversion Selection (CR2.EOCS).
bool VBATE
VBAT channel enable (ADC_CCR.VBATE).
ADC_Align ALIGN
Data alignment (CR2.ALIGN).
bool SCAN
Scan mode enable for regular channels (CR1.SCAN).
ADC_SequenceLength JL
Injected channel sequence length (1 to 4 conversions) (JSQR.JL).
uint16_t(* readData)(struct _ADC *adc)
Function pointer to read the ADC regular conversion result.
bool AWDEN
Analog Watchdog Enable on regular channels (CR1.AWDEN).
ADC_TypeDef * interface
Pointer to the STM32 ADC peripheral register map (e.g., ADC1).
bool AWDIE
Interrupt Enable for Analog Watchdog (CR1.AWDIE).
bool CONT
Continuous conversion mode for regular channels (CR2.CONT).
bool JAWDEN
Analog Watchdog Enable on injected channels (CR1.JAWDEN).
bool(* updateConfig)(struct _ADC *adc, ADC_Config *config)
Function pointer to update the ADC configuration.
ADC_Resolution RES
Resolution of the ADC (CR1.RES).
ADC_Channel SQ[16]
Regular channel sequence definition (SQ1 to SQ16) (SQR1, SQR2, SQR3).
ADC_SampleTime SMP[19]
Sampling time for each channel (0-18) (SMPR1, SMPR2).
bool JEOCIE
Interrupt Enable for End Of Injected Conversion (CR1.JEOCIE).
ADC_Channel JSQ[4]
Injected channel sequence definition (JSQ1 to JSQ4) (JSQR).
ADC_Channel AWDCH
Analog Watchdog Channel Select (if AWDSGL is true) (CR1.AWDCH).
bool TSVREFE
Temperature sensor and VREFINT enable (ADC_CCR.TSVREFE).
ADC_SequenceLength L
Regular channel sequence length (1 to 16 conversions) (SQR1.L).
uint16_t HTR
Analog watchdog higher threshold (HTR). Value should be 12-bit.
ADC_t ADC_init(ADC_TypeDef *adc_regs, ADC_Config *config)
ADC_SampleTime
ADC channel sample time enumeration.
uint16_t ADC_readData(ADC_t *adc)
Reads the data from the last ADC regular conversion.
ADC_Resolution
ADC conversion resolution enumeration.
ADC_Prescale
ADC prescaler selection enumeration.
ADC_Align
ADC data alignment enumeration.
bool ADC_startConversion(ADC_t *adc, ADC_ConversionType type)
Starts a regular ADC conversion.
bool ADC_updateConfig(ADC_t *adc, ADC_Config *config)
Update ADC peripheral configuration.
ADC_SequenceLength
ADC regular channel sequence length enumeration.
ADC_ConversionType
ADC conversion type enumeration.
ADC_Channel
ADC input channels enumeration.
ADC_EocSelect
ADC End of Conversion (EOC) selection enumeration.
@ ADC_SMP_144
144 ADC clock cycles
@ ADC_SMP_112
112 ADC clock cycles
@ ADC_SMP_84
84 ADC clock cycles
@ ADC_SMP_480
480 ADC clock cycles
@ ADC_SMP_3
3 ADC clock cycles
@ ADC_SMP_15
15 ADC clock cycles
@ ADC_SMP_28
28 ADC clock cycles
@ ADC_SMP_56
56 ADC clock cycles
@ ADC_RES_6
6-bit resolution
@ ADC_RES_8
8-bit resolution
@ ADC_RES_10
10-bit resolution
@ ADC_RES_12
12-bit resolution
@ ADC_ADCPRE_PCLK2_DIV6
ADCCLK = PCLK2 divided by 6.
@ ADC_ADCPRE_PCLK2_DIV4
ADCCLK = PCLK2 divided by 4.
@ ADC_ADCPRE_PCLK2_DIV8
ADCCLK = PCLK2 divided by 8.
@ ADC_ADCPRE_PCLK2_DIV2
ADCCLK = PCLK2 divided by 2.
@ ADC_ALIGN_RIGHT
Data is right-aligned in the ADC_DR register.
@ ADC_ALIGN_LEFT
Data is left-aligned in the ADC_DR register.
@ ADC_L1
1 conversion in the regular sequence
@ ADC_L5
5 conversions in the regular sequence
@ ADC_L9
9 conversions in the regular sequence
@ ADC_L6
6 conversions in the regular sequence
@ ADC_L11
11 conversions in the regular sequence
@ ADC_L8
8 conversions in the regular sequence
@ ADC_L10
10 conversions in the regular sequence
@ ADC_L14
14 conversions in the regular sequence
@ ADC_L2
2 conversions in the regular sequence
@ ADC_L12
12 conversions in the regular sequence
@ ADC_L15
15 conversions in the regular sequence
@ ADC_L7
7 conversions in the regular sequence
@ ADC_L3
3 conversions in the regular sequence
@ ADC_L16
16 conversions in the regular sequence
@ ADC_L4
4 conversions in the regular sequence
@ ADC_L13
13 conversions in the regular sequence
@ ADC_CONVERSION_REGULAR
Start a regular group conversion.
@ ADC_CONVERSION_INJECTED
Start an injected group conversion.
@ ADC_IN7
Analog input channel 7.
@ ADC_IN16
Analog input channel 16.
@ ADC_IN15
Analog input channel 15.
@ ADC_IN6
Analog input channel 6.
@ ADC_IN0
Analog input channel 0.
@ ADC_IN8
Analog input channel 8.
@ ADC_IN17
Analog input channel 17.
@ ADC_IN9
Analog input channel 9.
@ ADC_IN14
Analog input channel 14.
@ ADC_IN11
Analog input channel 11.
@ ADC_IN13
Analog input channel 13.
@ ADC_IN18
Analog input channel 18.
@ ADC_IN3
Analog input channel 3.
@ ADC_IN12
Analog input channel 12.
@ ADC_IN10
Analog input channel 10.
@ ADC_IN1
Analog input channel 1.
@ ADC_IN2
Analog input channel 2.
@ ADC_IN4
Analog input channel 4.
@ ADC_IN5
Analog input channel 5.
@ ADC_EOCS_SEQUENCE
EOC flag is set at the end of a sequence of regular conversions.
@ ADC_EOCS_SINGLE
EOC flag is set at the end of each single regular conversion.
ADC configuration structure.
Struct definition for ADC interface. Provides the API handle for consumers to interact with an ADC pe...